1. Field of the Invention
The present invention relates to a double-diffused, insulated-gate, field effect transistor.
2. Description of the Prior Art
FIGS. 1(A) and 1(B) show a known double-diffused, insulated-gate, field effect transistor. As shown in these figures, the transistor comprises a semiconductor substrate consisting of N.sup.+ semiconductor layer 1a and N.sup.- semiconductor layer 1b formed on the layer 1a. Layer 1b acts as a drain region. Channel base regions 2 of the P conductivity type are formed in layer 1b, spaced apart from each other. Narrow region 3, generally called a neck area, is provided between regions 2. Source electrode 5 is buried in insulating layer 4 overlying channel base regions 2. Gate electrode 6 is formed in insulating layer 4 and overlies region 3.
Let us assume that a power MOSFET having a high reverse bias voltage of hundreds of volts (e.g., 400 V) of the structure described above is manufactured. The conduction path 100 of this power MOSFET is prominently narrowed due to the broadening of a depletion layer formed in narrow region 3. This increases the ON resistance of the power MOSFET. Hence, the magnitude of the ON current of the MOSFET is about ten times lower than that of a power MOSFET having a lower reverse bias voltage of, for example, 60 V, provided the narrow regions of the power MOSFET are of equal size. One solution of this problem is to broaden region 3. This solution results in a decrease of effective channel width per unit area. This decrease does not occur in the MOSFET shown in FIG. 2, wherein N.sup.+ impurity area 8 having the same diffusion depth as channel base regions 2 is formed in narrow region 9 present between regions 2.
The MOSFET of FIG. 2 has a drawback, however. Since entire region 8 is an N.sup.+ type region, the source-to-drain reverse bias voltage, V.sub.DSS, is determined by channel base regions 2 and N.sup.+ impurity area 8. Hence, the MOSFET cannot have a high reverse bias voltage. To raise the reverse bias voltage, depletion layer 7 must be formed below narrow region 3, thus floating the potential of impurity area 8. This method improves the ON characteristic of the MOSFET, as experimentally proved, but narrow area 9 is left between depletion layer 7, immediately below N.sup.+ region 8.
Hitherto it has been possible to solve the above-noted problem completely.